![]() |
|
|
|||||||
![]() |
VHDL - design of 2-bit adder in tree format |
|
|
Thread Tools | Search this Thread |
|
|
#1 |
|
I am trying to design a 2-bit adder in tree format. The design looks like as: Four 2-bit Full adders at top, than three 3-bit FA at second stage, than 2 4-bit FA at third stage. In final single 5-bit FAs.
2-bit FA with 3-bit output is developed by considering carry-out as data bit. 1. Problem is how to develop other 3 2-bit FA in single row? 2. & than float the output arguments of first row i.e. sum0[0..2], sum1[0...2], sum2[0...2], sum3[0...2] as inputs for the next row having 3 3-bit FA. & so on. final shape of the design will look like a traingle. Could any one helpout in this regad? shan shan |
|
|
|
|
![]() |
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Error: Physical sythesis tool PALAC is not supported by Formal Verification tool Conf | bbiandov | Software | 0 | 12-22-2008 05:25 AM |
| Why No One Wins in the High-Def Format War | Ablang | DVD Video | 50 | 11-04-2007 04:19 AM |
| As growth slows, Hollywood faces a DVD standoff. | Allan | DVD Video | 0 | 07-11-2005 02:10 PM |
| High Definition and the future of viewing. | Allan | DVD Video | 3 | 03-09-2005 12:56 AM |
| Format Wars Redux: Blu-ray Disc vs. HD-DVD | Ablang | DVD Video | 2 | 02-20-2005 08:06 AM |