vhdl vector subtraction

Hi i have this code that doesn't work:


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


V_NEW_1 <= V_STORE_1 - GRAD_NORM_1;

where all are: SIGNAL std_logic_vector (7 down to 0)

and this warning:

There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

Someone can help me?
thanks

nicx82

[jeppe]

How about giving then an init value like
Signal V_NEW1: std_logic_vector (7 downto 0) := "00000000";

Jeppe

jeppe

[nicx82]

thanks for the reply.

nicx82

[nicx82]

By initializing the vectors the code works, but V_NEW_1 take the value of V_STORE_1 and not the value of the difference beetween V_STORE_1 and GRAD_NORM_1.

V_NEW_1 <= (V_STORE_1 - GRAD_NORM_1);

nicx82

[jeppe]

Well - I got a feeling - the REAL problem could be - GRAND_NORM_1 never given a value in your circuit.
Please check this
Jeppe

jeppe