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vhdl vector subtraction

 
 
nicx82 nicx82 is offline
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Join Date: Nov 2008
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      11-05-2008
Hi i have this code that doesn't work:


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


V_NEW_1 <= V_STORE_1 - GRAD_NORM_1;

where all are: SIGNAL std_logic_vector (7 down to 0)

and this warning:

There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

Someone can help me?
thanks
 
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jeppe jeppe is offline
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Join Date: Mar 2008
Location: Denmark
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      11-05-2008
How about giving then an init value like
Signal V_NEW1: std_logic_vector (7 downto 0) := "00000000";

Jeppe
 
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nicx82 nicx82 is offline
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      11-05-2008
thanks for the reply.
 

Last edited by nicx82; 11-05-2008 at 02:55 PM..
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nicx82 nicx82 is offline
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      11-05-2008
By initializing the vectors the code works, but V_NEW_1 take the value of V_STORE_1 and not the value of the difference beetween V_STORE_1 and GRAD_NORM_1.

V_NEW_1 <= (V_STORE_1 - GRAD_NORM_1);
 
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jeppe jeppe is offline
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      11-05-2008
Well - I got a feeling - the REAL problem could be - GRAND_NORM_1 never given a value in your circuit.
Please check this
Jeppe
 
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