library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 Uncomment the following library declaration if instantiating
 any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ADD1 is
Port ( AX : in STD_LOGIC_VECTOR (3 downto 0);
BX : in STD_LOGIC_VECTOR (3 downto 0);
AY : in STD_LOGIC_VECTOR (3 downto 0);
BY : in STD_LOGIC_VECTOR (3 downto 0);
AZ : in STD_LOGIC_VECTOR (3 downto 0);
BZ : in STD_LOGIC_VECTOR (3 downto 0);
CX : out STD_LOGIC_VECTOR (7 downto 0);
CY : out STD_LOGIC_VECTOR (7 downto 0);
CZ : out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end ADD1;
architecture Behavioral of ADD1 is
type state_type is (S0, S1, S2, S3);
signal state: state_type;
signal X1, Y1, Z1, X2, Y2, Z2: std_logic_vector (3 downto 0);
signal X3, Y3, Z3: std_logic_vector (7 downto 0);
begin
add_state: process (clk, reset) is
begin
if reset ='1' then
state <= S0;
elsif (clk'event and clk ='1') then
case state is
when S0 =>
X1 <= AX; Y1 <= AY; Z1 <= AZ;
X2 <= BX; Y2 <= BY; Z2 <= BZ;
state <= S1;
when S1 =>
X3 <= X1 + X2;
state <= S2;
when S2 =>
Y3 <= Y1 + Y2;
state <= S3;
when S3 =>
Z3 <= Z1 + Z2;
state <= S0;
end case;
end if;
end process add_state;
CX <= X3; CY <= Y3; CZ <= Z3;
end Behavioral;
this is my VHDL code..however...when i try to run the testbench...it poped up this error msg...
"Target Size 8 and source size 4 for array dimension 1 does not match."
What does it means actually??
