That is excellent news, well done to you and the Accellera team!
As you mentioned we *all* need to speak to our vendors/distributors to get
this standard adopted as quick as possible. The process is simple, send them
an email asking for an Enhancement Request (ER) to get this standard
Make sure you get an ER or equivalent number this to make sure you request
is in "the system" and doesn't get lost
If you want to be specific (better) just check out some of the new features
from Jim's presentation or the Doulos website and ask the vendor to
"Jim Lewis" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ine...
> Just a quick update on 1076-2008. We have completed
> all balloting and REVCOM has approved the standard.
> The final step is for the IEEE tech pubs department
> to put it into their format for publishing.
> I will give you a further update when you can get a
> copy from IEEE. In the mean time, you can get papers
> from SynthWorks' website: http://www.synthworks.com/papers
> There are two books you can purchase from Elsevier:
> VHDL-2008, Just the New Stuff by Peter Ashenden and Jim Lewis
> THE DESIGNER'S GUIDE TO VHDL, 3rd Edition, by Peter Ashenden
> Since most of these features are also part of Accellera
> VHDL Draft 3.0 (we viewed this as a trial standard on the road
> to making the VHDL revision), there is no reason not to submit
> bug reports to your vendors now requesting your favorite
> features to be implemented - please be specific as they
> tend to do the things asked for most first.
> -------- Original Message --------
> Subject: 1076-2008 - Approval Notification
> Date: Wed, 8 Oct 2008 17:15:58 -0400
> From: @ieee.org
> To: http://www.velocityreviews.com/forums/(E-Mail Removed)
> 8 October 2008
> Jim Lewis
> SynthWorks Design Inc
> 11898 SW 128th Ave
> Tigard, OR 97223
> cc: Victor Berman, C/DA Liaison
> Michael Kipness, Program Manager
> Kim Breitfelder, Manager -- Standards Editing and Production
> RE: REVISION P1076/D4.3a (C/DA) Standard VHDL Language Reference Manual
> Dear Jim,
> Editorial staff has informed me that the copyright requirements for
> P1076 were met on 26 September 2008. Therefore, the condition for
> approval has been fulfilled, and the approval date will be recorded as
> 26 September 2008.
> Moira Patterson
> Administrator, Governance; IEEE-SA
> 445 Hoes Lane
> Piscataway, NJ 08854
> IEEE. Fostering technological innovation and excellence for the benefit
> of humanity.
> As you mentioned we *all* need to speak to our vendors/distributors to get
> this standard adopted as quick as possible. The process is simple, send them
> an email asking for an Enhancement Request (ER) to get this standard
The more realistic way to get features implemented is to ask smaller
features which are really needed. Asking for the whole standard will
make the enhancement very big task, and when the work amount is big
and priority is low it won't get implemented.
It took years to get the SystemVerilog completely implemented to the
>I have already asked Mentor several times to look at this standard,
>unfortunately according to a Mentor engineer I am one of the few who
>has done this,
They already have some preliminary support. Read the
"Kim Enkovaara" <(E-Mail Removed)> wrote in message
news:OXBHk.77838$(E-Mail Removed). fi...
> HT-Lab wrote:
>> As you mentioned we *all* need to speak to our vendors/distributors to
>> get this standard adopted as quick as possible. The process is simple,
>> send them an email asking for an Enhancement Request (ER) to get this
>> standard implemented.
> The more realistic way to get features implemented is to ask smaller
> features which are really needed.
I agree, hence I wrote "better" between brackets.
> Asking for the whole standard will
> make the enhancement very big task, and when the work amount is big
> and priority is low it won't get implemented.
Perhaps, however, from a marketing point of view it makes very little sense
to implement just one feature. What they want is to be able to say, we
support VHDL-2008 standard, which is slighly better than saying we support
only case? from the VHDL2008 standard
> It took years to get the SystemVerilog completely implemented to the
This is a silly comparison, have you ever seen the SystemVerilog LRM? it is
absolutely massive and it dwarfs the VHDL-2008 enhancements. If you look at
Modelsim most (if not all) of the enhancements are already available in one
way or another. The only problem for companies like Mentor is that they need
to implement the standard across a number of products (Modelsim, Precision,
HDL Designer) and I suspect this is going to take time.
> >I have already asked Mentor several times to look at this standard,
> >unfortunately according to a Mentor engineer I am one of the few who has
> >done this,
> They already have some preliminary support. Read the
Have you? I checked it out when it first became available and was highly
disappointed. The enhancements are nothing more than supporting the
fixed/floating point package (without any waveform support!) and a simple
VHDL package for the Verilog $finish task.