I'm trying to describe an encoder in behavioral style. This is my vhdl code:

Code:

entity encoder is
generic(N: integer:=3);
port(i1: in bit_vector(2**N-1 downto 0);
o1: out bit_vector(N-1 downto 0));
end encoder;
architecture behavioral of encoder is
begin
process(i1)
variable k: integer;
begin
k:=0;
while k<2**N and i1(k)='0' loop
k:=k+1;
end loop;
if k=2**N then
o1 <= (others => '0') after 5 ns;
else
for i in 0 downto N-1 loop
if (k mod 2)=1 then
o1(i) <= '1' after 5 ns;
else
o1(i) <= '0' after 5 ns;
end if;
k:=k/2;
end loop;
end if;
end process;
end behavioral;

This is my testbench:

Code:

entity encoder_tb is
generic(
N : INTEGER := 3 );
end encoder_tb;
architecture TB_ARCHITECTURE of encoder_tb is
component encoder
generic(
N : INTEGER := 3 );
port(
i1 : in BIT_VECTOR(2**N-1 downto 0);
o1 : out BIT_VECTOR(N-1 downto 0) );
end component;
signal i1 : BIT_VECTOR(2**N-1 downto 0);
signal o1 : BIT_VECTOR(N-1 downto 0);
begin
UUT : encoder
generic map (
N => N
)
port map (
i1 => i1,
o1 => o1
);
i1 <= "00000000",
"10000000" after 100 ns,
"01000000" after 200 ns,
"00100000" after 300 ns,
"00010000" after 400 ns,
"00001000" after 500 ns,
"00000100" after 600 ns,
"00000010" after 700 ns,
"00000001" after 800 ns,
"10100100" after 900 ns,
"00001000" after 1000 ns,
"00100111" after 1100 ns,
"11111111" after 1200 ns;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_encoder of encoder_tb is
for TB_ARCHITECTURE
for UUT : encoder
use entity work.encoder(behavioral);
end for;
end for;
end TESTBENCH_FOR_encoder;

When I simulate the output is always "000". Debugging my code I saw that when the condition in the "if" is false, the "for" in the "else" doesn't execute, but I don't understand the reason!

Why doesn't it work?