Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Generic Component Instantiation

Reply
Thread Tools

Generic Component Instantiation

 
 
minhajhassan minhajhassan is offline
Junior Member
Join Date: Sep 2008
Posts: 1
 
      09-26-2008
I am instantiating a module N number of times, each time with different parameters as shown

Gen_LUTs: for i in 0 to N-1 generate
LUTs: LUT_generic generic map (LUT_Size(i),Log_Size(i),LUT_Width(i))
port map(....
Where LUT_Size, Log_Size, LUT_Width are arrays of integers.
The port sizes of IN/Outs depends upon the generics

How should the component be instantiated in the declarative part. Without i.
If not possible is there any better way to do this?
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Explicit instantiation of STL vector demands explicit instantiation of all the templates it using internally. krunalbauskar@gmail.com C++ 1 12-25-2006 03:51 PM
Instantiation of lots of the some component Cor van Loos VHDL 2 12-09-2004 05:53 AM
Questions about Timing analysis and Component Instantiation. systolic VHDL 1 11-29-2004 03:18 PM
component instantiation with generic parameter defined within a file Louis Dupont VHDL 2 08-31-2004 04:34 AM
how to prevent component instantiation every time? Jim Hammond ASP .Net 4 11-11-2003 07:49 PM



Advertisments
 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57