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Can port Maps be expressions?

 
 
Shannon
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      09-24-2008
Does VHDL allow expressions in port maps? For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
PORT MAP(
clock => MClk,
cnt_en => lockout_cnt_en AND NOT lockout_eq0,
data => STD_LOGIC_VECTOR(LOCKOUT_TIME),
sload => lockout_sload,
q => lockout_cnt
);

Shannon
 
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Shannon
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      09-24-2008
On Sep 24, 9:08*am, Alan Fitch <(E-Mail Removed)> wrote:
> Shannon wrote:
> > Does VHDL allow expressions in port maps? *For example see 'cnt_en'
> > below:

>
> > lockout_count: ENTITY work.counter_16
> > * *PORT MAP(
> > * *clock * * * * * => MClk,
> > * *cnt_en * * * * *=> lockout_cnt_en AND NOT lockout_eq0,
> > * *data * * * * * *=> STD_LOGIC_VECTOR(LOCKOUT_TIME),
> > * *sload * * * * * => lockout_sload,
> > * *q * * * * * * * => lockout_cnt
> > * *);

>
> > Shannon

>
> No, not currently
>
> Alan
>
> P.S. The feature is introduced in VHDL2008 which should be standardised
> by the IEEE this year.
>
> --
> Alan Fitch
> Douloshttp://www.doulos.com


Thank you.
 
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Andy
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      09-26-2008
On Sep 25, 3:48*am, Alan Fitch <(E-Mail Removed)> wrote:

The "type conversion" need not be just a type conversion. It must be a
function with exactly one argument, and the return type of the
function must be constrained.

For example, invert(lockout_time) would also work, if invert() returns
a constrained type. The data type need not actually change.

The same restriction applies to a type conversion, unless it is an
implicit conversion (e.g. from numeric_std.unsigned to SLV).

I saw a paper several years ago that used conversion functions in
configuration port maps to allow substitution of integer vs vector
based models.

Andy
 
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