Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > a small vhdl problem

Reply
Thread Tools

a small vhdl problem

 
 
s_hlu s_hlu is offline
Junior Member
Join Date: Sep 2008
Location: Germany
Posts: 1
 
      09-24-2008
Hallo,
I am new to vhdl, now met a problem and dont know how to solve..
I am implementing somelike Bitwise Arbitration in can bus, now on my bus interface i have 2 ports, txd_o and rxd_i.(one for transmit, one for receive).
Now i wanna do something like : if(txd_o /= rxd_i) , then sth bla bla.. ----------Now so the problem is obviously that, synthesis says, Object txd_o of mode OUT cannot be read
So does anyone know, how to solve this ? Or has some more better ideas to implement this ? (Bitwise Arbitration need to compare the value this node sent and the value this node read )
Thanks a lot !

Regards,
 
Reply With Quote
 
 
 
 
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      09-24-2008
Try to change OUT with INOUT - this will normally solve the problem
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Emacs VHDL-Mode Problem : vhdl-update-sensitivity-process omara007 VHDL 0 01-06-2010 03:47 AM
Small problem in VHDL zhe VHDL 2 10-06-2008 03:15 AM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
Small cameras getting too small? GRL Digital Photography 50 02-03-2006 03:12 AM
Small Square with small red X Peter Coddington Computer Support 4 01-03-2006 06:58 AM



Advertisments