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Re: Why does the placement of a statement mater in vhdl, I thought itwas a parallel language ?

 
 
ghelbig
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      09-18-2008
On Sep 17, 10:20 pm, "Morten L. Haugen" <(E-Mail Removed)>
wrote:
> Why does the placement of a statement mater in vhdl, I thought it was a
> parallel language )-:
>
> What vhdl mechanism occurs when the placement of a statement (before or
> after an if statement) makes a complete different result in a clocked
> process? First process below generates a flip-flop for rd_1_en, while the
> second process below generates just a constant '1' for rd_2_en.
>
> Seems to be valid construction, checked with modelsim, synplify, Xilinx XST.
>
> I guess its delta delays defining what happens, any body who understand this
> in detail?
>
> Same result in all tools?
>
> p_one_ff : process(clk)
>
> begin
>
> if rising_edge(clk) then
>
> rd_1_en <= '1'; -- statement in question !!!!!!!!
>
> if (sel_low = '1') then
>
> rd_1_en <= '0';
>
> end if;
>
> end if;
>
> end process p_one_ff;
>
> p_constant_1 : process(clk)
>
> begin
>
> if rising_edge(clk) then
>
> if (sel_low = '1') then
>
> rd_2_en <= '0';
>
> end if;
>
> rd_2_en <= '1'; -- statement in question !!!!!!!!
>
> end if;
>
> end process p_constant_1;
>
> Morten L. Haugen,
>
> GE Vingmed Ultrasound, Norway


You are getting exactly the results I would expect.

In each process you have two assignments to the same signal. The
assignments will be done from top to bottom, just like any other
procedural language.

Your first process has a common method for avoiding latches; set every
signal in the process at the beginning, then change some of them
according to conditions.

(BTW, Verilog behaves the same way.)

Hope that helps,
G.
 
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