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Can anyone please help me fix the error ? I am trying to compile the
code with Modelsim PE Student Edition 6.4
and i am getting an error :
# Compile of test.vhd failed with 1 errors.

vcom -work work -2002 -explicit F:/new/test.vhd
Model Technology ModelSim PE Student Edition vcom 6.4 Compiler 2008.05
Jun 30 2008
-- Loading package standard
** Error: F:/new/test.vhd(2): near "EOF": syntax error

This is the code :-


entity Counter_1 is end;
library STD;
use STD.TEXTIO.all;

architecture Behave_1 of Counter_1 is
-- declare a signal for the clock ,type BIT , initial Value '0'
signal Clock : BIT := '0' ;
-- declare a signal for the count Type INTEGER , initial value 0
signal Count : INTEGER := 0 ;
begin
process
begin -- process to generate a clock
wait for 10 ns; -- a delay of 10 ns is half the clock cycle
Clock <= not Clock;
if ( now > 340 ns ) then wait; end if; -- stop after 340 ns
end process;
-- process to do the counting ,runs concurrently with the other processes

process
begin
-- wait until the clock goes from 1 to 0
wait until ( Clock = '0');
-- now handle the counting
if ( Count = 7 ) then Count <= 0;
else Count <= Count + 1;
end if ;
end process;

process (Count) variable L: LINE ;
begin -- process to print
write (L, now); write (L , STRING'("Counter = "));
write (L, Count); writeline(output , L);
end process;
end;


Regards
Tarique

"Tarique" <> wrote in message news:gajlu3$ulk$...
> Can anyone please help me fix the error ? I am trying to compile the code
> with Modelsim PE Student Edition 6.4
> and i am getting an error :
> # Compile of test.vhd failed with 1 errors.
>
> vcom -work work -2002 -explicit F:/new/test.vhd
> Model Technology ModelSim PE Student Edition vcom 6.4 Compiler 2008.05 Jun
> 30 2008
> -- Loading package standard
> ** Error: F:/new/test.vhd(2): near "EOF": syntax error
>
> This is the code :-
>
>
> entity Counter_1 is end;
> library STD;
> use STD.TEXTIO.all;
>
> architecture Behave_1 of Counter_1 is
> -- declare a signal for the clock ,type BIT , initial Value '0'
> signal Clock : BIT := '0' ;
> -- declare a signal for the count Type INTEGER , initial value 0
> signal Count : INTEGER := 0 ;
> begin
> process
> begin -- process to generate a clock
> wait for 10 ns; -- a delay of 10 ns is half the clock cycle
> Clock <= not Clock;
> if ( now > 340 ns ) then wait; end if; -- stop after 340 ns
> end process;
> -- process to do the counting ,runs concurrently with the other processes
>
> process
> begin
> -- wait until the clock goes from 1 to 0
> wait until ( Clock = '0');
> -- now handle the counting
> if ( Count = 7 ) then Count <= 0;
> else Count <= Count + 1;
> end if ;
> end process;
>
> process (Count) variable L: LINE ;
> begin -- process to print
> write (L, now); write (L , STRING'("Counter = "));
> write (L, Count); writeline(output , L);
> end process;
> end;
>
>
> Regards
> Tarique

Add the following statement at the end
end Behave_1;

The structure of an architecture is of the form...
architecture Arbitray_Name_Of_Architecture of Entity_Name is
-- signal names here
begin
end Arbitray_Name_Of_Architecture;

KJ