Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Re: Are Xilinx tools that bad, or am I missing something?

Reply
Thread Tools

Re: Are Xilinx tools that bad, or am I missing something?

 
 
Rich Webb
Guest
Posts: n/a
 
      09-07-2008
On 06 Sep 2008 17:04:58 -0700, thutt <(E-Mail Removed)> wrote:

>Hi,
>
>I've got a design that is in working order, albeit with a little more
>diagnostic signals still in the source than I really want. I am using
>the Xilinx Spartan 3E board, and I tend to use the on-board LEDs for
>diagnostic purposes.
>
>To that end, I have an entity which controls the PS/2 keyboard
>connected to my home brew computer with the following declaration:
>
> entity harp_keyboard_controller is
> generic (clock_rate : natural); -- clock speed in Hz
> port(clk : in std_logic;
> --->>> kbd_leds : out std_logic_vector(7 downto 0);
> kbd_clk : inout std_logic; -- keyboard clock signal
> kbd_data : inout std_logic; -- keyboard data signal
> interrupt : out boolean;
> reset : in std_logic;
> enable : in boolean;
> write : in boolean;
> address : in std_logic_vector(1 downto 0);
> data_size : in ram_types.memory_size_t;
> data_write : in std_logic_vector(7 downto 0);
> data_read : out std_logic_vector(7 downto 0);
> ready : out boolean);
> end entity harp_keyboard_controller;
>
>The 'kbd_leds' output signal was used for diagnostics, but is no
>longer needed.

[snip...snip...]
>It's only when I remove the signal declaration from
>'harp_keyboard_controller' that the project fails to function
>properly.
>
>I'm a software guy trying to do things with hardware,


#include <std_disclaimer>

Me too, so maybe some of my own recent faux pas may be relevant.

> and while I've
>learned a lot in the past 18 months, I am confounded by what appears
>to be lack of quality in the Xilinx toolchain. It doesn't seem to me
>that removing a completely unused signal should have an affect on the
>resulting synthesized hardware.


This is somewhat of a swag but I note that kbd_leds isn't a signal, it's
one of the black box's I/O ports and hooked up to the device pins (I
guess "to its balls" is more correct, still ...). Are they still
floorplanned in your user constraints file after removing them from the
port definition?

--
Rich Webb Norfolk, VA
 
Reply With Quote
 
 
 
 
Muzaffer Kal
Guest
Posts: n/a
 
      09-07-2008
On 06 Sep 2008 20:12:16 -0700, thutt <(E-Mail Removed)> wrote:
>The 'signal' at the top level isn't removed, it's still present and
>quasi-used. It works like this:
>
> -- S3E demo board has 4 slider switches & 8 LEDs.
> -- I combine the switches and the LEDs to get 16 banks of 8 LEDs.
> -- I have an array, 16 x 8 of std_logic which corresponds to the
> LED values.
> -- The bank of LEDs which is actively connected to the actual
> on-board LEDs is selected by the slider switches.
>
>The signal which was assigned to the output port of the
>'harp_keyboard_controller' entity was one element of the 16-element
>array. That element of the array was not used for anything else in
>the design -- it's just for outputting the most recent byte received
>from the attached PS2 keyboard.
>
>At the point that I removed the assignment to the output port in the
>top level design, the 'harp_keyboard_controller' did not use the port
>at all -- it did not assign anything to it at all; it was completely
>unused.
>
>So, I just don't understand why removing a port that it unused can
>make the design fail.


I have one question and a suggestion. What exactly do you mean by
"project ... fails to function properly" ? What parts of it break
down? That may help to figure out what's going on.
The suggestion is based on an assumption. If you left the switch
selection still at the keyboard output, does it help to change it to
another of the 16 possibilities?

--
Kal
 
Reply With Quote
 
 
 
 
Muzaffer Kal
Guest
Posts: n/a
 
      09-07-2008
On 06 Sep 2008 20:12:16 -0700, thutt <(E-Mail Removed)> wrote:
>The 'signal' at the top level isn't removed, it's still present and
>quasi-used. It works like this:
>
> -- S3E demo board has 4 slider switches & 8 LEDs.
> -- I combine the switches and the LEDs to get 16 banks of 8 LEDs.
> -- I have an array, 16 x 8 of std_logic which corresponds to the
> LED values.
> -- The bank of LEDs which is actively connected to the actual
> on-board LEDs is selected by the slider switches.
>
>The signal which was assigned to the output port of the
>'harp_keyboard_controller' entity was one element of the 16-element
>array. That element of the array was not used for anything else in
>the design -- it's just for outputting the most recent byte received
>from the attached PS2 keyboard.
>
>At the point that I removed the assignment to the output port in the
>top level design, the 'harp_keyboard_controller' did not use the port
>at all -- it did not assign anything to it at all; it was completely
>unused.
>
>So, I just don't understand why removing a port that it unused can
>make the design fail.


I have one question and a suggestion. What exactly do you mean by
"project ... fails to function properly" ? What parts of it break
down? That may help to figure out what's going on.
The suggestion is based on an assumption. If you left the switch
selection still at the keyboard output, does it help to change it to
another of the 16 possibilities?

--
Kal
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
problem in running a basic code in python 3.3.0 that includes HTML file Satabdi Mukherjee Python 1 04-04-2013 07:48 PM
Re: Are Xilinx tools that bad, or am I missing something? Sean Durkin VHDL 4 09-10-2008 09:27 PM
QUES: Where can I find Xilinx M1 tools Ted VHDL 6 01-21-2004 03:18 PM



Advertisments