hi steff,

ur attempt to help is greatly appreciated ....i have tried the line u just has edited now :

sum <= "00"&NBC(0)+"00"&NBC(1)+"00"&NBC(2)+"00"&NBC(3 );

but after introducing a new intermediate signal ...>>>

i wrote the code as follows:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity test is

port (

NBC :in std_logic_vector(3 downto 0);

op

ut std_logic_vector(2 downto 0)

);

end test;

architecture arch of test is

signal sum :unsigned (2 downto 0);

signal sum_un :unsigned(3 downto 0);

begin

sum_un<=unsigned(NBC);

sum <= ("00"&sum_un(0))+

("00"&sum_un(1))+

("00"&sum_un(2))+

("00"&sum_un(3 ));

op <= std_logic_vector(sum);

end arch;

Also i have tried to remove this signal ....as u suggested and it worked....i dont know the impact on the synthesis but i'll discover soon ..

thanks for ur help steff

bye