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VHDL - MOD function

 
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Old 09-03-2008, 10:55 PM   #1
Default MOD function


I'm intend to write a MOD function with two positive integer number.
It could be synthesized but cannot be simulated.
It would be very appreciated if anyone could tell me how to write:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package mymod_pack is

function mymod ( L, R : in integer ) return integer;

end mymod_pack;


package body mymod_pack is

function mymod ( L, R : in integer ) return integer is
variable tmp : integer;
begin
tmp := L;
if L > R then
while tmp > R loop
tmp := L - R;
end loop;
elsif L < R then
tmp := L;
elsif L = R then
tmp := 0;
else tmp := 0;
end if;
return tmp;
end function;

end mymod_pack;


timewing
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