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VHDL - strange function"std_logic_vector" |
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hi,every one. I found a strange funtion in package "ieee.unsigned_std ";
like following: ---------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package STD_LOGIC_UNSIGNED is ..... function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR (length-1 downto 0); begin result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus return std_logic_vector(result); end; ....... ---------------------------------------------------------------- do you notice the line"return std_logic_vector(result);"? "result" is the type of unsigned,and it is converted to the type of std_logic_vector.But, where does the function "std_logic_vector(arg: unsigned)" come from? I have looked for it in IEEE.std_logic_1164 and IEEE.std_logic_arith, and did not found it. If I want to convert unsigned type to std_logic_vector,can I just do it in this way " std_logic_vector(result)", and needn't to use the function of conv_std_logic_vector which is in the package of ieee.std_logic_arth? guaji Last edited by guaji : 09-03-2008 at 10:40 AM. |
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