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VHDL - Is it correct to build a LFSR?

 
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Old 08-30-2008, 09:47 PM   #1
Default Is it correct to build a LFSR?


I'm intend to build a LFSR, and assign the first 576 states to an array. The taps I choose is [16, 14, 13, 11]

There's the warning:
Register <rom<1>> equivalent to <rom<0>> has been removed
Register <rom<2>> equivalent to <rom<0>> has been removed
...
Register <rom<576>> equivalent to <rom<0>> has been removed

I guess there's something wrong with my code?




type rom_type is array(0 to 576) of bit_vector(15 downto 0);

constant allzero : bit_vector(15 downto 0) := (others => '0');
signal q : bit_vector(15 downto 0) := (others => '1');
signal reset : std_logic;

signal rom : rom_type;

begin

reset <= '1' when q = allzero else '0';

process (reset) is

variable tmp : rom_type;

begin
if (reset='1') then
q <= (others => '1'); ----seed of the LFSR
else
for i in rom_type'range loop
q(0) <= q(15) xor q(13) xor q(12) xor q(10);
q(15 downto 1) <= q(14 downto 0);
tmp(i) := q;
end loop;
rom <= tmp;
end if;
end process;


timewing
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