CAN Bus opencore in Verilog... lpm_ram_dp problem

I've downloaded the CAN Bus opencore in Verilog format but I encounter some difficulties to simulate the core with ModelSim Altera web edition.

As soon as I want to simulate my testbench with "vsim" command, Modelsim says:


** Error: (vsim-3033) D:/00 - Harware Project/can/rtl/verilog/can_fifo.v(291): Instantiation of 'lpm_ram_dp' failed. The design unit was not found.
# Region: /can_testbench/i_can_top2/i_can_bsp/i_can_fifo
# Searched libraries:
# work

So, it seems to search the "work" library but if I type "vlib work", I see this message:

# ** Warning: (vlib-34) Library already exists at "work".

Where is the problem?! I really need to simulate the code to help me to understand how it work!!!

Thanks in advance!

jgauthier68