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VHDL - Re: Use for 'simple_name attribute |
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Reuven wrote:
> i've used the 'simple_name attribute in the following manner: > ... > and the name v_my_var changed, then nothing ( except the keen eyes of > the coder ) would prevent the printed variable label from remaining > the outdated name. > Any comments? I would prefer to use a simulation wave or list for debugging or an assertion for verification. -- Mike Treseler Mike Treseler |
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