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VHDL - Re: Mixed clocked/combinatorial coding styles |
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On Aug 18, 11:53 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote: > I have been able to try this on five different > synthesis tools, spanning the whole range of > cost and FPGA-vs-ASIC. The results surprised > me a little - it's a long time since I did such > a complete survey. .... > Comments welcomed. > -- Jonathan, This is interesting, but I'm not sure exactly what conclusions to draw. At least, no incorrect logic was generated (sighs of relief from vendors involved). This smells like it could turn into a hunt for cases which *do* mess up synthesizers, but that's a lot of experimenting. This is also interesting in that you've performed experiments, guided by some hypotheses, and examined the results in light of those hypotheses. Smells a bit like the scientific method to me. Clearly, you don't get this usenet thing at all - Kenn kennheinrich@sympatico.ca |
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