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VHDL----"type" error

 
 
benghwee8 benghwee8 is offline
Junior Member
Join Date: Aug 2008
Posts: 2
 
      08-18-2008
entity RAM_TEST is
generic
(
B : natural := 9
);

port
(
ADD : in natural range 0 to 2**B - 1;
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT: out std_logic_vector (15 downto 0);

);
end RAM_TEST
architecture RAM_TEST_arch of RAM_TEST is

-- Build a 2-D array type for the RAM
type MEMORY is array(ADD'high downto 0) of std_logic_vector(15 downto 0);

-- Declare the RAM signal.
signal RAM : MEMORY;

begin
.......................
........................
RAM(ADD) <= DATA_IN
......................



Hi, I am trying to write some commads to build ram, above are the commands.
However, I have met an error from simulator:
1st. This error mentions that the 'type' syntax cannot support the prefix like "ADD'high", any suggestion to correct this?
 
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