Real port types in VHDL

Hello all,

Which VHDL simulator with waveform analyzer supports real type ports?
Both ModelSim and NCSIM allow real type computations but are shy of
the real type ports.

Yaseen

yaseenzaidi@netzero.com

Alan Fitch wrote:

> Here's my code which works,

It does, but why the break with local traditions?

I inserted a few of these: report (real'image(o));
and I can see it in text:

# vsim -c etb
# Loading work.etb(bench)
# Loading work.real_port(synth)
VSIM 1> run
# ** Note: -1.000000e+308
# Time: 0 ns Iteration: 0 Instance: /etb
# ** Note: 0.000000e+00
# Time: 10 ns Iteration: 0 Instance: /etb
# ** Note: 2.420000e+00
# Time: 20 ns Iteration: 0 Instance: /etb
VSIM 2>

Thanks for the posting.

-- Mike Treseler

Mike Treseler