How to declare a real type port in the entity?

hello everyone, i am a beginner,i want to convert integer to float.
in my designed entity, i declare a real type port in the entity:

entity to_fp is
port (vec: in std_ulogic_vector(15 downto 0);
r: out real);
end entity to_fp;

but when i analysis and synthesis the entity,the quartus ii give the message:

Error (10414): VHDL Unsupported Feature error at to_fp.vhd(4): cannot synthesize non-constant real objects or values

could you tell me how to deal with the error message,and How to declare a real type port in the entity?

thanks a lot.

patrick1018

[jeppe]

The short version
You can only use the type real in connection with a simulation

Jeppe

jeppe