Frequency divider with clk en.

want to make a frequency divider (50 Mhz to any value, 560khz ), I am working with a counter like a freq. divider but there is a warning in Quartus II:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

I read that using a CLK EN is the best way to make a freq. divider, but a I don't know nothing about it, DO YOU HAVE INFORMATION OR EXAMPLES ABOUT? HELP ME PLEASE

chema15

[jeppe]

Hopefully will this appear useful:
your welcome¨
Jeppe

PHP Code:

entity Freqency_divider is
    Port (     Clkin : in  STD_LOGIC;
                Clkout : inout  STD_LOGIC := '0');
end Freqency_divider;

-- How to avoid clockskew in logic designs
architecture Behavioral of Freqency_divider is
    signal Enable: std_logic;
begin
    process(Clkin)-- All processes should use the same clock
        variable Scale_counter: integer range 0 to 2000000;
    begin
        if rising_edge(Clkin) then
            if Scale_counter < 1500000 then -- Random value
                Scale_counter := Scale_counter+1;
                Enable <= '0';
            else
                Scale_counter := 0;
                Enable <= '1';        -- Must only be '1' for one clkin cycle
            end if;
        end if;
    end process;
    
    process(Clkin)        -- All processes should use the same clock
    begin
        if rising_edge( Clkin) then
            if Enable='1' then            -- heres the "trick"
                Clkout <= not Clkout;    -- Do something
            end if;
        end if;
    end process;

end Behavioral; 


jeppe