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Frequency divider with clk en.

 
 
chema15 chema15 is offline
Junior Member
Join Date: Jul 2008
Posts: 2
 
      08-12-2008
want to make a frequency divider (50 Mhz to any value, 560khz ), I am working with a counter like a freq. divider but there is a warning in Quartus II:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

I read that using a CLK EN is the best way to make a freq. divider, but a I don't know nothing about it, DO YOU HAVE INFORMATION OR EXAMPLES ABOUT? HELP ME PLEASE
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      08-13-2008
Hopefully will this appear useful:
your welcomeš
Jeppe

PHP Code:
entity Freqency_divider is
    Port 
(     Clkin in  STD_LOGIC;
                
Clkout inout  STD_LOGIC := '0');
end Freqency_divider;

-- 
How to avoid clockskew in logic designs
architecture Behavioral of Freqency_divider is
    signal Enable
std_logic;
begin
    process
(Clkin)-- All processes should use the same clock
        variable Scale_counter
integer range 0 to 2000000;
    
begin
        
if rising_edge(Clkinthen
            
if Scale_counter 1500000 then -- Random value
                Scale_counter 
:= Scale_counter+1;
                
Enable <= '0';
            else
                
Scale_counter := 0;
                
Enable <= '1';        -- Must only be '1' for one clkin cycle
            end 
if;
        
end if;
    
end process;
    
    
process(Clkin)        -- All processes should use the same clock
    begin
        
if rising_edgeClkinthen
            
if Enable='1' then            -- heres the "trick"
                
Clkout <= not Clkout;    -- Do something
            end 
if;
        
end if;
    
end process;

end Behavioral
 
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