Simulation of VHDL code in ISE

Dear friends,
I am new to VHDL. Can you please tell me how to simulate a program like below.

entity coeff_ram is
port ( rd, wr : in bit;
addr : in integer range 0 to 63;
d_in : in real; d_out : out real );
end entity coeff_ram;

architecture abstract of coeff_ram is
begin

memory : process (rd, wr, addr, d_in) is

type coeff_array is array (0 to 63) of real;

variable coeff : coeff_array := (others => 0.0);

begin
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end process memory;
end architecture abstract;

My intention is to read and write into the memory. but while simulation addr is not an integer.Its an array of lenght 64. So obviously it throws and error that the limit of Coeff array is exeeding. Can you please help me in simulating the code?

rangaprasad