attributes in VHDL

can anybody tell me that: attributes can be converted into signals or
not.

shweta

No. They can't.
Signals can have attributes but attributes are not signals.

On Aug 7, 10:31*pm, shweta <shwetadeshmuk...@gmail.com> wrote:
> can anybody tell me that: attributes can be converted into signals or
> not.

TigerJade

On 8 Aug, 08:56, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Thu, 7 Aug 2008 22:48:22 -0700 (PDT), TigerJade wrote:
> >Signals can have attributes but attributes are not signals.
>
> Just to be nit-picky: *for user-defined attributes
> you are indeed right, but some of the built-in
> attributes of signals are signals themselves.
> For a signal S...
>
> * S'delayed(time_value) *is a signal of the same type as S;
> * S'transaction * * * * *is a signal of type BIT;
>
> and there may be a couple of others that don't spring
> to mind right now. *Naturally, these being built-in
> attributes there's nothing you can do to alter the
> way they behave.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Using my Doulos VHDL Golden Reference Guide, arnt all signal specific
attributes signals themselves?

From the list:
S'Delayed(time)
S'Stable(time)
S'Quiet(time)
S'Transaction
S'Event
S'Active
S'Last_event
S'last_active
S'Last_value
S'Driving
S'Driving_name

Tricky

On Aug 8, 9:57 am, Tricky <Trickyh...@gmail.com> wrote:
> On 8 Aug, 08:56, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > On Thu, 7 Aug 2008 22:48:22 -0700 (PDT), TigerJade wrote:
> > >Signals can have attributes but attributes are not signals.
>
> > Just to be nit-picky: for user-defined attributes
> > you are indeed right, but some of the built-in
> > attributes of signals are signals themselves.
> > For a signal S...
>
> > S'delayed(time_value) is a signal of the same type as S;
> > S'transaction is a signal of type BIT;
>
> > and there may be a couple of others that don't spring
> > to mind right now. Naturally, these being built-in
> > attributes there's nothing you can do to alter the
> > way they behave.
> > --
> > Jonathan Bromley, Consultant
>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
>
> Using my Doulos VHDL Golden Reference Guide, arnt all signal specific
> attributes signals themselves?
>
> From the list:
> S'Delayed(time)
> S'Stable(time)
> S'Quiet(time)
> S'Transaction
> S'Event
> S'Active
> S'Last_event
> S'last_active
> S'Last_value
> S'Driving
> S'Driving_name

Not quite. For example, S'Event is of function kind, so you get a
value from it but can't do signal-specific things to that value. For
example s'event'delayed is not defined, whereas s'stable(1 ns)'delayed
would be defined.

Delayed, stable, transaction, quiet, are the only four predefined
attributes of signal kind.

Taking a wild guess as to interpreting the OP's question, none of
these attributes, even though they are signals according to the
language semantics, will ever turn into synthesizable signals (i.e.
"wires" in the FPGA or ASIC sense).

- Kenn

kennheinrich@sympatico.ca