Register bank with multiple ports

I wonder whether any of you knows a vhdl template for a register bank with multiple ports. Actually I am thinking of something like one port for writing into the bank and four ports for reading. R/W access will be exclusive. The four read ports might read at the same time but on different addresses.
Not that I am lazy, I am thinking quite a while about a slick solution but got somehow stuck, resp. feel quite unsatisfied with a brute force approach with five case block accessing some register array...but maybe thats the best idea...
Any hints you can give?

Thanxalot

eko