Velocity Reviews > VHDL > binary to bcd conversion (12 bit to 4 digit)

# binary to bcd conversion (12 bit to 4 digit)

raja_bade
Junior Member
Join Date: May 2008
Posts: 2

 07-31-2008
Dear friends, May this code help people who need bin to bcd.. Algorithm used is shift and add3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bintobcd is
Port ( bindata : in STD_LOGIC_VECTOR (11 downto 0);
clk : in STD_LOGIC;
reset: in std_logic;
t11,t22,t33,t44: out integer);
end bintobcd;

architecture Behavioral of bintobcd is
signal temp: std_logic_vector(11 downto 0):="000000000000";
signal temp1: std_logic_vector(15 downto 0):="0000000000000000";
signal shcntr: integer:=0;
--signal i1,i2,i3,i4: integer:=0;
signal state: integer range 0 to 5;
begin
--
process
begin
wait until clk='1';

case state is

when 0 => if reset='0' then
temp<=bindata;
shcntr<=0;
temp1<=(others =>'0');
state<=1;
end if;

when 1 => if shcntr/=12 then
temp1<=temp1(14 downto 0) & temp(11);
temp<=temp(10 downto 0) & '0';
shcntr<=shcntr+1;
state<=2;
end if;

when 2=> if shcntr<12 then
if temp1(3 downto 0)>="0101" then
state<=3;
elsif temp1(7 downto 4)>="0101" then
state<=4;
elsif temp1(11 downto >="0101" then
state<=5;
else
state<=1;
end if;
else
state<=0;
end if;

when 3=> temp1(3 downto 0)<=temp1(3 downto 0)+"0011";
if temp1(7 downto 4)>="0101" then
temp1(7 downto 4)<=temp1(7 downto 4)+"0011";
state<=1;
elsif temp1(11 downto >="0101" then
temp1(11 downto <=temp1(11 downto +"0011";
state<=1;
else
state<=1;
end if;

when 4=> temp1(7 downto 4)<=temp1(7 downto 4)+"0011";
if temp1(11 downto >="0101" then
temp1(11 downto <=temp1(11 downto +"0011";
state<=1;
elsif temp1(3 downto 0)>="0101" then
temp1(3 downto 0)<=temp1(3 downto 0)+"0011";
state<=1;
else
state<=1;
end if;

when 5=> temp1(11 downto <=temp1(11 downto +"0011";
if temp1(3 downto 0)>="0101" then
temp1(3 downto 0)<=temp1(3 downto 0)+"0011";
state<=1;
elsif temp1(7 downto 4)>="0101" then
temp1(7 downto 4)<=temp1(7 downto 4)+"0011";
state<=1;
else
state<=1;
end if;

end case;
end process;
process(shcntr,clk)
begin
if shcntr=12 then
if clk'event and clk='1' then
t44<=conv_integer(temp1(15 downto 12));
t33<=conv_integer(temp1(11 downto );
t22<=conv_integer(temp1(7 downto 4));
t11<=conv_integer(temp1(3 downto 0));
end if;
end if;
end process;

end Behavioral;

jeppe
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348

 07-31-2008
This VHDL code look more like a program for a CPU and the same is true for the algoritm. Its bound to give you problems as you noticed.

Try to visit this page for inspiration. A conversion like of 12bit binary to 4xbcd can be done with 12 clock pulses.

http://jjmk.dk/MMMI/Lessons/06_Arith...sion/Index.htm

Your welcomeš
Jeppe

raja_bade
Junior Member
Join Date: May 2008
Posts: 2

 07-31-2008
Thanks for the inspirational link... But it is a stepping stone for beginners who strike bottle necks during a design testing phase..

code has no problems and it is synthesized on spartan II fpga

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