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two related process

 
 
lucianofalbo lucianofalbo is offline
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Join Date: Jul 2008
Location: pavia
Posts: 22
 
      07-28-2008
Hi. I have not experience in vhdl but i need to make work this code! It is very important!
I explain the problem. I have a 24 bits vector as input (B). The input dataready is a signal that is high when B must be read(it is a strobe). I want that the output signal Bup is a 1 microsecond pulse only when B increases. clk50 is a 50 MHz clock. On the contrary these two my processes give 1 microsecond pulses but not always and something also when B does not increase.
WHY???????Thank you very much for your help

rst<=dataready;
gatepr: process (B,dataready,rst)
variable lastB : std_logic_vector (23 downto 0);
begin
if rst='0' then
up<='0';
elsif (dataready'event and dataready = '1') then
if B>lastB then
up<='1';
end if;
Bdiff<=B-lastB;
lastB:=B;
end if;
end process gatepr;

spero: process(up,clk50)
variable conta: integer:=51;
variable last_up: std_logic;
begin
if clk50'event and clk50='1' then
if (up='1' and last_up='0') then
conta:=0;
elsif conta<50 then
Bup<='1';
elsif conta>=50 then
Bup<='0';
end if;
last_up:=up;
conta:=conta+1;
end if;
end process spero;
 

Last edited by lucianofalbo; 07-28-2008 at 05:15 PM..
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jeppe jeppe is offline
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Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      07-29-2008
Not sure - but try this:
spero: process(up,clk50)
variable conta: integer:=51;
variable last_up: std_logic;
begin
if clk50'event and clk50='1' then
if (up='1' and last_up='0') then
conta:=0;
end if;
if conta<50 then
Bup<='1';
elsif conta>=50 then
Bup<='0';
end if;
last_up:=up;
conta:=conta+1;
end if

Your welcome
Jeppe
 
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lucianofalbo lucianofalbo is offline
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      07-29-2008
DEar Jeppe thanks but your code does not work. I had already tried in that way.
thanks
 
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jeppe jeppe is offline
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      07-29-2008
Ok one more try - its very hot outside today - better in the shadow

gatepr: process (B,dataready,rst)
variable lastB : std_logic_vector (23 downto 0);
begin
if rst='0' then
up<='0';
elsif (dataready'event and dataready = '1') then
up<='0'; -- default setting
if B/=lastB then
up<='1';
end if;
Bdiff<=B-lastB;
lastB:=B;
end if;
end process gatepr;

Hope this works better
 
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lucianofalbo lucianofalbo is offline
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Join Date: Jul 2008
Location: pavia
Posts: 22
 
      07-29-2008
Unfortunately your new code does not work. I am aware that the problem is mainly (only?) in this process (gatepr). The problem with your code and my code is that sometimes I have not the pulse. Furthermore another very strange behaviour is this one: I send a B waveform to the FPGA and after the waveform has finished I continue sending the last value. Then I have pulses during I am sending the last value(B is constant!) . What can be the problem? Maybe the rst I use?
(I use rst<=dataready outside the process) or the comparation B>lastB?
All the others elements seem to me very standard things. Or not? what do you think?
Thanks
 
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jeppe jeppe is offline
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Posts: 348
 
      07-29-2008
Ok - I "cleaned" your code a bit - hopefully will this do the trick
PHP Code:
begin
    gatepr
process (dataready)
        
variable lastB std_logic_vector (23 downto 0);
    
begin
        
if (dataready'event and dataready = '1') then 
            up <= '
0';
            if B/=lastB then 
                up <= '
1';
            end if; 
            Bdiff<=B-lastB;
            lastB:=B; 
        end if; 
    end process gatepr; 

    spero: process(clk50)
        variable conta: integer:=51;
        variable last_up: std_logic;
    begin
        if clk50'
event and clk50='1' then
            
if (up='1' and last_up='0'then 
                conta
:=0;
            
end if;
            
Bup<='0';
            if 
conta<50 then
               conta
:=conta+1;
               
Bup<='1';
            
end if;    
            
last_up:=up;
        
end if; 
    
end process spero;
    
end Behavioral
 
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lucianofalbo lucianofalbo is offline
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      07-29-2008
I have used your new code(I have done copy and paste from your post)but it works worst than the others: I have only few pulses and not always in the same positions.
Thanks for your past and future attempts.
 
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jeppe jeppe is offline
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Posts: 348
 
      07-29-2008
Well well - have you tried to make a sketch of the signals your planningto messure.

You must consider how often the dataready changes etc.
May be its not possible to do, what your want to do.

Some of the signals you generates with the two processes could may be better be incorperated "closer" to the "B" counter.

A simulation (with downscaled clk signals etc) could give you some hints but still if your problems "noise" will a simulation not help you.

A hard one indeed
 
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lucianofalbo lucianofalbo is offline
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Join Date: Jul 2008
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      07-29-2008
Dataready is 300 kHz signal that is high for about 1.6 microsecond. It becomes high about 10 nsec the new B is ready. clk50 is a 50 MHz signal. Why do you think this could be a problem?
 
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jeppe jeppe is offline
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Join Date: Mar 2008
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Posts: 348
 
      07-30-2008
My final solution - I believe a single FSM must be the best way to avoid timing, glitches or what ever the "real" problem.

PHP Code:
entity FSM_solution1 is
    Port 
Clk50MHz :  in  STD_LOGIC;
           
Reset :     in  STD_LOGIC;
           
Dataready in  STD_LOGIC;
           
:         in  STD_LOGIC_VECTOR (23 downto 0);
           
Bup :       out  STD_LOGIC);
end FSM_solution1;

architecture Behavioral of FSM_solution1 is
    type   States is 
(Detect_Dataready0,Detect_Dataready1Test_BMake_Bup_Puls);
    
signal State:   States;
    
signal Counterinteger range 0 to 63;
    
signal Last_B:  STD_LOGIC_VECTOR (23 downto 0); 
    
begin
    process
Clk50MHz)
    
begin
        
if rising_edgeClk50MHzthen
            
if Reset='1' then
                State  
<= Detect_Dataready0;
                
Bup    <= '0';
                
Last_B <= B;
            else
                case 
State is
                    when Detect_Dataready0 
=>
                        
Bup <= '0';
                        if 
Dataready='0' then
                            State 
<= Detect_Dataready1;
                        
end if;
                    
when Detect_Dataready1 =>
                        
Bup <= '0';
                        if 
Dataready='1' then
                            State 
<= Test_B;
                        
end if;
                    
when Test_B =>
                        
Bup <= '0';    
                        if 
B/=Last_B then
                            Counter 
<= 1;
                            
State <= Make_Bup_Puls;
                        else
                            
State <= Detect_Dataready0;
                        
end if;
                        
Last_B <= B;
                    
when Make_Bup_Puls =>
                        
Counter <= Counter+1;
                        
Bup <= '1';
                        if 
Counter 49 then
                            State   
<= Detect_Dataready0
                        
end if;
                
end case;
            
end if;
        
end if;
    
end process;
end Behavioral
Your welcome
Jeppe
 

Last edited by jeppe; 07-30-2008 at 11:01 AM..
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