Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > two related process

Reply
Thread Tools

two related process

 
 
lucianofalbo lucianofalbo is offline
Junior Member
Join Date: Jul 2008
Location: pavia
Posts: 22
 
      08-04-2008
Yes, I have used the code @#18(in the week end I can't use the FPGA). Dataready is the clock of the vector B. I have not understood your last suggestion. I can't take the B value at the falling edge of dataready because this means a delay of 1.5 microsecond. B is not an increasing vector: sometimes it increases sometimes it decreases, sometimes it is constant. What did you mean?
 
Reply With Quote
 
 
 
 
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      08-04-2008
Well I try to figure out what makes the B change value. It seams the problem could be rapid changes of B.
So there could be two possible uses of Dataready.
1) B will only change/remain constant due to Dataready.
2) B change totally random and Dataready indicates its time to check B.

Have you ever watched the B vector with ChipScope - a XiLinx software product which enables you to watch signals inside a FPGA.
 
Reply With Quote
 
 
 
 
lucianofalbo lucianofalbo is offline
Junior Member
Join Date: Jul 2008
Location: pavia
Posts: 22
 
      08-04-2008
No I have never used chipScope. I have seen the different bits of B by a Scope
and B changes at the frequency of dataready that becomes high more or less 20-30 nsec after B has changed. So dataready says me when considering B new value.
 
Reply With Quote
 
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      08-04-2008
Ok - let me put it this way:
After an rising_edge of Dataready should the B values be stable after some time - may be should the statemachine collect the B values and for them to settle.
 
Reply With Quote
 
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      08-04-2008
How about this - I will try a simulation later.

PHP Code:
entity Test2 is
    Port 
(    Clk50 :       in   STD_LOGIC;
                
Reset :       in   STD_LOGIC;
                
DataReady :   in   STD_LOGIC;
                
:           in   STD_LOGIC_VECTOR (23 downto 0);
                
BupBenable :out  STD_LOGIC);
end Test2;

architecture Behavioral of Test2 is
    type       States is 
(Detect_Dataready0,Detect_Dataready1Test_for_stable_B
                                
Test_BMake_Bup_Puls); 
    
signal     State:   States
    
signal     Counterinteger range 0 to 63
    
signal     NewB1,NewB2,Last_B:    STD_LOGIC_VECTOR (23 downto 0);
    
signal   Sync_B:         STD_LOGIC_VECTOR (23 downto 0);  
    
signal     Sync_DataReadySTD_LOGIC;
    
constant Bminstd_logic_vector (23 downto 0) := "000011001010101111110011";
    
constant Bmaxstd_logic_vector (23 downto 0) := "000011011001110110010001"
    
begin
   
    Syncronize
processClk50)  -- THIS PROCESS TOO MAKE EVENTUALLY ASCYNCRONE SIGNALSSYNCRONE WITH Clk50
    begin
        
if Rising_edge(Clk50then
            Sync_B            
<= B;
            
Sync_DataReady <= DataReady;
        
end if;
    
end process Syncronize;
    
    
FSMprocessClk50)
    
begin
        
if rising_edgeclk50then
            
if Reset='1' then
                State  
<= Detect_Dataready0;
                
Bup    <= '0';
            else
                case 
State is
                when Detect_Dataready0 
=>
                    
Benable <= '0';
                    
Bup <= '0';
                    if 
Sync_Dataready='0' then
                        State 
<= Detect_Dataready1;
                    
end if;
                
when Detect_Dataready1 =>
                    
Benable <= '0';
                    
Bup <= '0';
                    if 
Sync_Dataready='1' then
                        NewB1  
<= Sync_B;
                        
NewB2  <= NewB1;
                        
State  <= Test_For_Stable_B;
                    
end if;
                
when Test_for_Stable_B =>
                    
NewB1  <= Sync_B;
                    
NewB2  <= NewB1;
                    if 
NewB1 NewB2 then
                        State  
<= Test_B;
                    
end if;
                
when Test_B =>
                    ------------------------------------------------------
                    if ( 
NewB2 Bmin and NewB2<Bmax then
                        Benable 
<= '1';
                    else 
                        
Benable <= '0';
                    
end if;
                    -------------------------------------------------------
                    
Bup <= '0'
                    if 
NewB2 Last_B then 
                        Counter 
<= 1;
                        
State   <= Make_Bup_Puls;
                    else
                        
State <= Detect_Dataready0;
                    
end if;
                    
Last_B <= NewB2;
                
when Make_Bup_Puls =>
                    
Counter <= Counter+1;
                    
Bup <= '1';
                    if 
Counter 49 then
                        State 
<= Detect_Dataready0
                    
end if;
                
end case;
            
end if;
       
end if;
    
end process FSM;
    
end Behavioral
 

Last edited by jeppe; 08-04-2008 at 12:51 PM..
Reply With Quote
 
lucianofalbo lucianofalbo is offline
Junior Member
Join Date: Jul 2008
Location: pavia
Posts: 22
 
      08-04-2008
Always the same problem
 
Reply With Quote
 
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      08-05-2008
Hmmmmm
May be should you repeat the problem one more time - a way to find the solution

I wonder:
1) Will B always increment by 1, 2 3 or xx
2) Will B always form a slope until its return to its starting value.
3) Will the errors always occur at the same "places" or values
 
Reply With Quote
 
lucianofalbo lucianofalbo is offline
Junior Member
Join Date: Jul 2008
Location: pavia
Posts: 22
 
      08-06-2008
Dear Jeppe I apologize for the delay but from yesterday I am on holiday and I can't work on my FPGA project up to 25 August. Anyway I say you that:
1) B can increase or decrease of one bit or zero
2) I have to send a command to my B generator, after this command B increases or decreases for about 2 second and then it remains constant until I send a new command
3) With the last codes I have used the errors are always at the same places
For example When B decreses from 100000000000000 to
011111111111111 I have a Bup pulse but
it is wrong because B decreases and does not increase.
Bye
 
Reply With Quote
 
lucianofalbo lucianofalbo is offline
Junior Member
Join Date: Jul 2008
Location: pavia
Posts: 22
 
      09-05-2008
Dear Jeppe
I am happy to inform you that your last code with the FSM works properly!!!
I have discovered that I had a hardware problem in my B generator (the cable used for the data transmission caused some bits to be unstable). Solved that problem the code works well. Thanks to your codes I have understood problems of synchronization and so on.
Bye
 
Reply With Quote
 
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      09-06-2008
Your welcome
May be some the former version (and your first code) would work as well
Jeppe
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Question related to multiprocessing.Process Cen Wang Python 4 01-19-2013 11:27 AM
How to compare two SOAP Envelope or two Document or two XML files GenxLogic Java 3 12-06-2006 08:41 PM
How should multiple (related) projects be arranged (structured) and configured so that they can share code, have a related package structure and enable proper unittesting, and ensuring no namespace collisions ToddLMorgan@gmail.com Python 14 04-21-2006 04:03 PM
Does 'process having a jvm loaded' related to other java processes? Naresh Agarwal Java 1 06-30-2005 05:53 PM
How should threads be terminated? (related to 'Help with thread related tracebacks') Maxwell Hammer Python 7 06-18-2005 04:20 PM



Advertisments