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[kiranec2004]

Hi all,

I have a desing long back done and now i want it to work for one half more the frequency what it was working before so what i have to do??

The coding is done in VHDL and if i select a different FPGA is it ok or any design changes i have to make.

Thanks in advance
KSR

[jeppe]

Well - it depends mostly on which tools / ISE your using for the design.

1) You could try to optimize your design by making smart VHDL kode but in the end will the result depend at the synthesize tool

2) Check the settings of your ISE - choose optimize for speed.

3) Set up user-constrains for the timing
(this could be hard to do and give you a loooong excecution time as well)

your welcome
Jeppe