Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > mixing in and out in the declaration of a port

Thread Tools

mixing in and out in the declaration of a port

cvt cvt is offline
Junior Member
Join Date: May 2008
Posts: 2
Hallo everyone

I do not have a good VHDL reference manual yet so I need to post this simple question.

I want to declare a 32 bit port AD where bits 0 to 3 and bit 19 are outputs and the rest are inputs. Keep in mind that in my (User Constraints File .ucf) I have done the pin mapping separately for each pin. Example:

NET "AD<1>" LOC = "P199";
NET "AD<31>" LOC = "P65" ;

So what will the declaration look like.

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Declaration hides port port_name / Port port_name hidden by declaration in architecture Merciadri Luca VHDL 2 11-02-2010 08:23 PM
maxplusII error: a deferred constant declaration without a full declaration is not supported Noah VHDL 5 04-07-2006 02:34 PM
"virtual outside class declaration" and "declaration does not declare anything" kelvSYC C++ 6 05-17-2005 08:58 AM
Function declaration in class declaration Ovidesvideo C++ 4 12-10-2004 06:36 PM
Intel C++ 8.0 : declaration hides declaration Alex Vinokur C++ 4 04-05-2004 09:49 PM