Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > RAM with Fault model

Reply
Thread Tools

RAM with Fault model

 
 
o.tamimi@hotmail.co.uk
Guest
Posts: n/a
 
      06-25-2008
i would appreciate someone's help

i have to design a VHDL model describing RAM with two different fault
models, such as stuck at fault and coupling fault
the following code is for genric RAM model, i do not know how can i
optimise it so that a functional fault is injected
library ieee;
use ieee.std_logic_1164.all;


entity RAM8X8 is
port ( Address : in integer range 0 to 7;
Data : inout std_logic_vector (7 downto 0);
WE : in std_logic;
OE : in std_logic);
CS : in std_logic);


Architecture behaviour of SRAM8X8 is

Type RAM8X8_array is array (0 to 7) of std_logic_vector (7 downto
0);

Begin
Process (address,Data,WE,OE,CS ) is
Variable mem: RAM8X8_array;

Begin
Data<= (others => Z);
if CS=0 then
if OE=0 then
Data <= mem(Address);
Elseif WE=0 then
Mem(address):= Data;
End if;
End if;
End process;
End RAM8X8;

Many Thanks
Allan
 
Reply With Quote
 
 
 
 
KJ
Guest
Posts: n/a
 
      06-25-2008
On Jun 24, 8:06*pm, (E-Mail Removed) wrote:
> i would appreciate someone's help
>
> i have to design a VHDL *model describing RAM with two different fault
> models, such as stuck at fault and coupling fault
> the following code is for genric RAM model, i do not know how can i
> optimise it so that a functional fault is injected


Adding Data(0) <= '0'; at the end of your process creates a stuck at
'0' model.

Add a new variable called 'Address_faulty' like the following will
create another stuck at '0' model.
address_faulty := address - (address mod 2);
replace Mem(address) with Mem(address_faulty);

KJ
 
Reply With Quote
 
 
 
 
Marcus Harnisch
Guest
Posts: n/a
 
      06-30-2008
Hi Allan

http://www.velocityreviews.com/forums/(E-Mail Removed) writes:
> i have to design a VHDL model describing RAM with two different fault
> models, such as stuck at fault and coupling fault


Since you care about static faults only, I would generate them as part
of the write action. Although generating the error on read has the nice
side effect that you can tell what should have been returned. OTOH,
this violates the rule that checkers should be separated from models...

BTW: There are three different coupling faults. Check which type you
are supposed to implement.

Regards
Marcus

--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

(seen on http://www.veripool.com/verilog-mode_news.html)
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
[ANN] Falluto: A model checker for verifying fault tolerant systems Edgardo Hames Ruby 1 01-07-2010 03:47 AM
RAM with Fault model o.tamimi@hotmail.co.uk VHDL 0 06-25-2008 12:06 AM
Convert Java Model to Java Model without XML erinbot@gmail.com Java 1 10-06-2006 09:00 PM
Stack fault and page fault help S.Flournoy Computer Support 2 04-17-2004 04:23 PM
Looking for a VHDL or Verilog RAM Model that modles Common RAM Faults Robert Posey VHDL 0 11-26-2003 07:50 PM



Advertisments