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RAM with Fault model
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i would appreciate someone's help

i have to design a VHDL model describing RAM with two different fault
models, such as stuck at fault and coupling fault
the following code is for genric RAM model, i do not know how can i
optimise it so that a functional fault is injected
library ieee;
use ieee.std_logic_1164.all;

entity RAM8X8 is
port ( Address : in integer range 0 to 7;
Data : inout std_logic_vector (7 downto 0);
WE : in std_logic;
OE : in std_logic);
CS : in std_logic);

Architecture behaviour of SRAM8X8 is

Type RAM8X8_array is array (0 to 7) of std_logic_vector (7 downto

Process (address,Data,WE,OE,CS ) is
Variable mem: RAM8X8_array;

Data<= (others => Z);
if CS=0 then
if OE=0 then
Data <= mem(Address);
Elseif WE=0 then
Mem(address):= Data;
End if;
End if;
End process;
End RAM8X8;

Many Thanks
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