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Cadence compiler basics

 
 
PC
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      06-18-2008
Hi all,

I have a very very basic problem with the cadence VHDL compiler
For example

signal test : std_logic_vector( 15 downto 0);
begin

test<="1111111111111111" ; works fine
test<=x"ffff"; gives an error expecting an expression of type
STD_LOGIC_VECTOR 87[8.3] 93[8.4] why ?

thanks in advance
PC
 
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HT-Lab
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      06-18-2008

"PC" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> Hi all,
>
> I have a very very basic problem with the cadence VHDL compiler
> For example
>
> signal test : std_logic_vector( 15 downto 0);
> begin
>
> test<="1111111111111111" ; works fine
> test<=x"ffff"; gives an error expecting an expression of type
> STD_LOGIC_VECTOR 87[8.3] 93[8.4] why ?


The code is fine, try compiling with the VHDL93 standard,

Hans
www.ht-lab.com


>
> thanks in advance
> PC



 
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