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VHDL - timing in ISE Simulator

 
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Old 06-15-2008, 05:08 PM   #1
Default timing in ISE Simulator


Hello all,

i send two topic in this forum no one response.............

i wish any one reply me

i'm in abig problem...i use ISE simulator to simulate a circuit and i put input and recive the output i have an ambigity in two thing.....

first ,......timing report for the simulator ...where can i get it..
second,... are the next code true for a clock added to code or what??


entity Mult2 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
C : out STD_LOGIC_VECTOR (3 downto 0);
clk:in std_logic);
end Mult2;

architecture Behavioral of Mult2 is

begin
process(clk)
begin
if clk'event and clk='1' then
c(0)<=a(0) and b(0);
c(2)<=a(1) and b(1);
c1<=c(0) xor c(2) xor((b0 xor b1) and (a0 xor a1));
end if;
end process;
end Behavioral;


note: i want anyone to help me and contact him for some problems can anyone help me


samehsh
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