Resincronization problem: slow to fast domain

Hi all.
I'm thinking about resinchronize some signal of a slow time domain in a higher one.

In detail in a project I've 2 fifo written and readed with 3 different clock (first one is written with burst of 27Mhz and read with a 0.5Mhz, wheraes the second one is written with the 0.5Mhz and read with 5Mhz more or less).

No problem in doing it, but for detect some error in the stream I need to read fifo_empty and fifo_full of all this fifo with the 27Mhz.

I was thinking about doing it in this way:

fifo_signal_clk.clk <= not fifo_signal.clk;
fifo_signal_nclk <= fifo_signal;

fifo_signal_1_rclk.clk <= 27Mhz;
fifo_signal_2_rclk.clk <= 27Mhz;
fifo_signal_3_rclk.clk <= 27Mhz;
fifo_signal_1_rclk <= fifo_signal_nclk;
fifo_signal_2_rclk <= fifo_signal_1_rclk;
fifo_signal_3_rclk <= fifo_signal_2_rclk;

control.clk <= 27Mhz;
control <= fifo_signal_1_rclk XNOR fifo_signal_2_rclk;

fifo_usable_signal.clk <= 27Mhz;
fifo_usable_signal.ena <= control;
fifo_usable_signal <= fifo_signal_3_rclk;


What do you think?
Could be a way? Too much logic wasted?

mmarco76