Advice in testing a simple RAM code.

Hi,

I have written a simple RAM code in VHDL. It is just a simple code that Reads from the "Data" pin or writes to the "Data" pin. Because in VHDL, we are not able to see the info contains in the variable, I assign the info inside the variable "MEM_s" to output pin "DataOut" so that I can see its contents.

The code looks OK but when I tried to test it in Vector Waveform simulation, it doesn't seem to work.. Attached is the waveform before and after the simulation. From the waveform, it can be seen that whenever the "R_Wbar" pin is low (indicating reading from RAM), the "Data" pin is in high impedance state..
What I hope to be able to do is to first write something into Address "0000" of the RAM and after that read from the same location.

Below is the code..
Please advice how I can test it..

Thanks..

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM is 
	port ( 	A0,A1,A2,A3	:  in std_logic;
		   	CS		:  in std_logic;
		   	R_Wbar 	: in std_logic;
		   	Data 	: inout std_logic_vector (7 downto 0);
			DataOut	: out std_logic_vector (7 downto 0));
end RAM;

Architecture version1 of RAM is

	signal Addr : unsigned (3 downto 0);
	type MEM is array (15 downto 0) of std_logic_vector (7 downto 0);	
	signal MEM_s : MEM;
	
Begin

	Addr <= (A0 & A1 & A2 & A3);
	
	Process	(A0,A1,A2,A3,CS,R_Wbar,Data)
	
		variable Addr_int : integer;
	
	Begin
		--Addr_int := TO_INTEGER(Addr);
		if (CS = '1') then
	
			if (R_Wbar = '1') then 
			
				case Addr is
					when "0000" => MEM_s (0) <= Data;
					when "0001" => MEM_s (1) <= Data;
					when "0010" => MEM_s (2) <= Data;
					when "0011" => MEM_s (3) <= Data;
					when "0100" => MEM_s (4) <= Data;
					when "0101" => MEM_s (5) <= Data;
					when "0110" => MEM_s (6) <= Data;
					when "0111" => MEM_s (7) <= Data;
					when "1000" => MEM_s (8) <= Data;
					when "1001" => MEM_s (9) <= Data;
					when "1010" => MEM_s (10) <= Data;
					when "1011" => MEM_s (11) <= Data;
					when "1100" => MEM_s (12) <= Data;
					when "1101" => MEM_s (13) <= Data;
					when "1110" => MEM_s (14) <= Data;
					when "1111" => MEM_s (15) <= Data;
					when others => null;
				end case; 
				DataOut <= Data;
			elsif (R_Wbar = '0') then
				case Addr is
					when "0000" => Data <= MEM_s (0);
					when "0001" => Data <= MEM_s (1);
					when "0010" => Data <= MEM_s (2);
					when "0011" => Data <= MEM_s (3);
					when "0100" => Data <= MEM_s (4);
					when "0101" => Data <= MEM_s (5);
					when "0110" => Data <= MEM_s (6);
					when "0111" => Data <= MEM_s (7);
					when "1000" => Data <= MEM_s (8);
					when "1001" => Data <= MEM_s (9);
					when "1010" => Data <= MEM_s (10);
					when "1011" => Data <= MEM_s (11);
					when "1100" => Data <= MEM_s (12);
					when "1101" => Data <= MEM_s (13);
					when "1110" => Data <= MEM_s (14);
					when "1111" => Data <= MEM_s (15);
					when others => null;
				end case; 
				Data <= "11001100";
				DataOut <= Data;
			end if;
		
		end if;
	
	End process;
End version1;

Before Simulation


The waveform before and after simulation shows the same thing.

mrnobody