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VHDL - If statement with String condition

 
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Old 06-09-2008, 02:01 PM   #1
Default If statement with String condition


Hi everyone,
I would like to know how to do string comparison as a condition for if statement
for instance, i have a block with a string input (S) and it is being fed by either "sdfr23rdf34x23fsfdr" or "wedq23asd44x344dfd" and i would like to do the following
if (S == "sdfr23rdf34x23fsfdr")
.....
elsif (S=="wedq23asd44x344dfd")
..
end if;

could someone please help me about how to do such a comparison.


ROOZ
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Old 06-09-2008, 04:49 PM   #2
eko
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use strcmp(), can be found in library std_developerskit.std_iopak.all


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Old 06-10-2008, 02:03 PM   #3
ROOZ
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thanks eko for your response but I am having problem applying it.
i did the following

process

begin

if (strcmp(memory_model,"two_port_64x16")) then

inst_foundry_two_port_64x16b : TS6N65ULPA64X16M4F
................

end if ;
end process;

the problem is that i get the following error
No feasible entries for subprogram "strcmp".

and if i do the following,
process

begin

if ((strcmp(memory_model,"two_port_64x16"))==0) then

inst_foundry_two_port_64x16b : TS6N65ULPA64X16M4F
................

end if ;
end process;

i get another error
near "=": syntax error

could someone please help me with this.


ROOZ
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Old 06-10-2008, 03:39 PM   #4
mmarco76
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1- problem 1: be sure to have included the library.
In the beginning of the vhdl file you've to write:
use std_developerskit.std_iopak.all;

2- problem 2: in VHDL the comparison is only 1 "=" not "=="


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Old 06-10-2008, 05:08 PM   #5
ROOZ
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Quote:
Originally Posted by mmarco76
1- problem 1: be sure to have included the library.
In the beginning of the vhdl file you've to write:
use std_developerskit.std_iopak.all;

2- problem 2: in VHDL the comparison is only 1 "=" not "=="


thanks for the response but i realize the problem. i made my own strcmp function which is easier to use.


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