Clock divider?

Hi All,
could anyone suggest a code to create diffrent clock frequency from the main system clock? I wrote a code but it does not respond. Synthesizer does not implement "after" statement. (On the other hand In the simulation snapshot outputs are defined as U. Does It mean "undefined"?)
Waiting your valuable comments,
Thanks,
Oppenheimer


entity freqdiv is
Port ( clk : in STD_LOGIC;
freq1 : out STD_LOGIC;
freq2 : out STD_LOGIC;
freq3 : out STD_LOGIC);
end freqdiv;

architecture Behavioral of freqdiv is
signal div1,div2,div3: STD_LOGIC:= '0';
begin
freq1<= not clk after 25 us;
freq2<= not clk after 50 us;
freq3<= not clk after 75 us;

end Behavioral;
simulation.JPG

oppenheimer

[jeppe]

Seems you have to simulate at least 25 us before freq1 will get its first value - the figure above only shows 3 us.
Try to change us with ns for a special test.

Jeppe

jeppe

[oppenheimer]

Hi,

what is wrong on clock division code?

ERROR Notification is:
ERROR:Cpld:1235 - An illegal connection of the clock divider has been detected.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Sayici is
Port ( clk : in STD_LOGIC; --system clk
rst : in STD_LOGIC; --main reset
upbtn : in STD_LOGIC; --up buton
downbtn : in STD_LOGIC; --down buton
cs : out STD_LOGIC; --segment selector
data : out STD_LOGIC_VECTOR (6 downto 0)) ; --output data bus
end Sayici;

architecture Behavioral of Sayici is
signal Cclk,enb,scanclk: STD_LOGIC:= '0';
signal div1,div2,div3,div4: STD_LOGIC;
signal bcd,bcd1,bcd2: STD_LOGIC_VECTOR (3 downto 0) := "0000" ;

begin
process(clk)
begin
if rising_edge(clk) then
Cclk<= upbtn or downbtn or rst;
end if;
end process;

enb<= not Cclk and (upbtn or downbtn or rst);

process(clk)

begin
if rising_edge(clk) then
if enb= '1' then
if rst= '1' then
bcd1<= "0000";
bcd2<= "0000";
end if;

if UpBtn= '1' then
if bcd1= "1001" then
if bcd2= "1001" then
bcd1<= "0000";
bcd2<= "0000";
else
bcd2<= bcd2 + 1;
bcd1<= "0000";
end if;
else
bcd1<=bcd1 + 1;
end if;
end if;

if DownBtn= '1' then
if bcd1= "0000" then
if bcd2= "0000" then
bcd1<= "1001";
bcd2<= "1001";
else
bcd1<= "1001";
bcd2<= bcd2 - 1;
end if;
else
bcd1<=bcd1 - 1;
end if;
end if;
end if;
end if;

end process;

clk_div16_inst1 : clk_div16
port map (
clkdv => div1, -- Divided clock output
clkin => clk ); -- Clock input

clk_div16_inst2 : clk_div16
port map (
clkdv => div2, -- Divided clock output
clkin => div1 ); -- Clock input

clk_div16_inst3 : clk_div16
port map (
clkdv => div3, -- Divided clock output
clkin => div2 ); -- Clock input

clk_div16_inst4 : clk_div16
port map (
clkdv => div4, -- Divided clock output
clkin => div3 ); -- Clock input

process(div4)
begin
scanclk<= div4;
if scanclk= '0' then
bcd<= bcd1;
else
bcd<= bcd2;
end if;

case bcd2 is
when "0000" => Data<= "0111111";
when "0001" => Data<= "0000110";
when "0010" => Data<= "1011011";
when "0011" => Data<= "1001111";
when "0100" => Data<= "1100110";
when "0101" => Data<= "1101101";
when "0110" => Data<= "1111101";
when "0111" => Data<= "0000111";
when "1000" => Data<= "1111111";
when "1001" => Data<= "1101111";
when others => Data <= "1000000";
end case;
cs<= scanclk;
end process;

end Behavioral;

oppenheimer