Multiple errors in VHDL

I can't see where is the problem with this code. Can someone help me?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity Practica is

generic (N : integer range 0 to 16:=16);

port (
x : in STD_LOGIC_VECTOR (9 downto 0);
en_in : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (9 downto 0);
en_out: out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC);

end Practica;

architecture Behavioral of Practica is

--Senyals d'enable:
signal ena_comptN: STD_LOGIC;
signal ena_sum : STD_LOGIC;
signal ena_mult : STD_LOGIC;
signal ena_div : STD_LOGIC;

--Senyals de clear:
signal clr_comptN: STD_LOGIC;

--Senyal comptador:
signal Ns : integer range 0 to 16;
signal compt_r : STD_LOGIC;

--Senyals mult:
signal mult_out : STD_LOGIC_VECTOR (19 downto 0);
signal mult_in : STD_LOGIC_VECTOR (9 downto 0);
signal mult_r : STD_LOGIC;

--Senyals sumador:
signal add_m : STD_LOGIC_VECTOR (12 downto 0);
signal add_out : STD_LOGIC_VECTOR (9 downto 0);
signal add_r : STD_LOGIC;

--Senyals divisor:
signal div_out : STD_LOGIC_VECTOR (9 downto 0);
signal div_r : STD_LOGIC;

--Senyals de la maquina d'estats:
type estats is (e0,e1,e2,e3,e4,e5,e6,e7);
signal estat :estats;
signal proper_estat:estats;

--Senyals del registre:
signal r_x :STD_LOGIC_VECTOR (9 downto 0);


begin

reg_xrocess(clk,reset,en_in)
begin
if (reset='1') then
r_x <=(others=>'0');
elsif (clk'event and clk='1') then
if (en_in='1') then
r_x<=x;
end if;
end if;
end process;

mult_in<=r_x;


comptN: process(clk,clr_comptN,ena_comptN)
begin
if (clr_comptN='1') then
Ns<=0;
elsif (clk'event and clk='1') then
if (ena_comptN='1') then
Ns<=Ns+1;
end if;
end if;
end process;

mult: process(clk,mult_r,ena_mult)
begin
if (mult_r='1') then
mult_out<=(others=>'0');
elsif (clk'event and clk='1') then
if (ena_mult='1') then
mult_out <= mult_in*mult_in;
end if;
end if;
end process;

add: process(clk,add_r,ena_sum)
begin
if (add_r='1') then
add_m<=(others=>'0');
elsif (clk'event and clk='1') then
if (ena_sum='1') then
add_m<= add_m + (mult_out(1 & mult_out(1 & mult_out(1 & mult_out (18 downto 9));
end if;
end if;
end process;

add_out<=add_m(12 downto 3);

div: process(clk,div_r,ena_div)
begin
if (div_r='1') then
div_out<=(others=>'0');
elsif (clk'event and clk='1') then
if (ena_div='1') then
div_out<=add_out(9) & add_out(9) & add_out(9)& add_out(9)& add_out(9 downto 4);
end if;
end if;
end process;

y<=div_out;

maq_comb: process(estat, en_in)
begin
if (reset='1') then
proper_estat<=e0;
else
ena_mult <= '0';
ena_div <= '0';
ena_sum <= '0';
ena_comptN <= '0';
en_out <= '0';
clr_comptN<='0';
mult_r<='0';
add_r<='0';
div_r<='0';

case estat is
when e0 =>
mult_r<='1';
add_r<='1';
div_r<='1';
clr_comptN<='1';
if (en_in='1') then
proper_estat<=e1;
end if;
when e1 =>
ena_mult<='1';
if en_in='1' then
proper_estat<=e1;
end if;
when e2 =>
ena_sum<='1';
ena_mult<='1';
ena_comptN<='1';
if (Ns=16) then
proper_estat<=e3;
end if;
when e3 =>
ena_sum<='1';
proper_estat<=e4;

when e4 =>
ena_div<='1';
proper_estat<=e5;
when e5=>
proper_estat<=e6;
when e6=>
en_out<='1';
proper_estat<=e7;
when e7=>
proper_estat<=e0;

end case;
end if;
end process;

maq_sincrocess(clk)
begin
if (clk'event and clk='1') then
estat<=proper_estat;
end if;
end process;

end Behavioral;

Info: Duplicate registers merged to single register
Info: Duplicate register "div_out[6]" merged to single register "div_out[5]"
Info: Duplicate register "div_out[7]" merged to single register "div_out[5]"
Info: Duplicate register "div_out[8]" merged to single register "div_out[5]"
Info: Duplicate register "div_out[9]" merged to single register "div_out[5]"Warning: No clock transition on "Ns[0]" register due to stuck clock or clock enable
Warning: Reduced register "Ns[0]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "Ns[1]" register due to stuck clock or clock enable
Warning: Reduced register "Ns[1]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "Ns[2]" register due to stuck clock or clock enable
Warning: Reduced register "Ns[2]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "Ns[3]" register due to stuck clock or clock enable
Warning: Reduced register "Ns[3]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "Ns[4]" register due to stuck clock or clock enable
Warning: Reduced register "Ns[4]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[7]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[7]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[8]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[8]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[9]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[9]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[10]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[10]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[11]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[11]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[12]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[12]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[6]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[6]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[5]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[5]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[4]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[4]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[3]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[3]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[2]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[2]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[1]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[1]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "add_m[0]" register due to stuck clock or clock enable
Warning: Reduced register "add_m[0]" with stuck clock_enable port to stuck value GND
Warning: Reduced register "div_out[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "div_out[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "div_out[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "div_out[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "div_out[5]" with stuck data_in port to stuck value GND
Info: State machine "|Practica|estat" contains 8 states
Info: Selected Auto state machine encoding method for state machine "|Practica|estat"
Info: Encoding result for state machine "|Practica|estat"
Info: Completed encoding using 8 state bits
Info: Encoded state bit "estat.e7"
Info: Encoded state bit "estat.e6"
Info: Encoded state bit "estat.e5"
Info: Encoded state bit "estat.e4"
Info: Encoded state bit "estat.e3"
Info: Encoded state bit "estat.e2"
Info: Encoded state bit "estat.e1"
Info: Encoded state bit "estat.e0"
Info: State "|Practica|estat.e0" uses code string "00000000"
Info: State "|Practica|estat.e1" uses code string "00000011"
Info: State "|Practica|estat.e2" uses code string "00000101"
Info: State "|Practica|estat.e3" uses code string "00001001"
Info: State "|Practica|estat.e4" uses code string "00010001"
Info: State "|Practica|estat.e5" uses code string "00100001"
Info: State "|Practica|estat.e6" uses code string "01000001"
Info: State "|Practica|estat.e7" uses code string "10000001"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "y[0]" stuck at GND
Warning: Pin "y[1]" stuck at GND
Warning: Pin "y[2]" stuck at GND
Warning: Pin "y[3]" stuck at GND
Warning: Pin "y[4]" stuck at GND
Warning: Pin "y[5]" stuck at GND
Warning: Pin "y[6]" stuck at GND
Warning: Pin "y[7]" stuck at GND
Warning: Pin "y[8]" stuck at GND
Warning: Pin "y[9]" stuck at GND
Warning: Pin "en_out" stuck at GND
Warning: Design contains 13 input pin(s) that do not drive logic
Warning: No output dependent on input pin "x[9]"
Warning: No output dependent on input pin "x[8]"
Warning: No output dependent on input pin "x[7]"
Warning: No output dependent on input pin "x[6]"
Warning: No output dependent on input pin "x[5]"
Warning: No output dependent on input pin "x[4]"
Warning: No output dependent on input pin "x[3]"
Warning: No output dependent on input pin "x[2]"
Warning: No output dependent on input pin "x[1]"
Warning: No output dependent on input pin "x[0]"
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "en_in"
Warning: No output dependent on input pin "reset"

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