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#1 | |
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How to...?
Quote:
thx. sonaj |
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#2 |
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Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 245
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; .... dac: out std_logic; signal dac_count: std_logic_vector (5 downto 0); if dac_count>conv_std_logic_vector(24,6) then dac<= dac_data(conv_integer(dac_count)); -- May be OK dac_cs<='0'; else dac<='0'; dac_cs<='1'; end if; jeppe |
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#3 |
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Junior Member
Join Date: Jun 2008
Posts: 3
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Not found abel style equations list FPGA project, only CPLD project.
Xilinx ISE 10.1 I am beginer, and that list helps very much for me. sonaj |
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