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06-02-2008, 09:10 PM
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#1 |
clock divider
How do I design a clock divider without using initial conditions. I
designed once using initial values but they dont mean anything in synthesis. Thanks in advance for your help FP |
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06-02-2008, 09:12 PM
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#2 |
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Posts: n/a
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Re: clock divider
On Jun 2, 4:10*pm, FP <FPGA.unkn...@gmail.com> wrote:
> How do I design a clock divider without using initial conditions. With a reset signal. > I designed once using initial values but they dont mean anything in > synthesis. > If your targetted part has a specified power up state and the tools that you choose to use support initial values then initial values will work just fine. KJ KJ |
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