On Jun 9, 2:28 pm, Mike Treseler <(E-Mail Removed)> wrote:

> rickman wrote:

> > ---No matching overload for "/="---

>

> > DataOutReg is slv and CTPCurCmd is unsigned. I thought that the two

> > types were "closely related" which means I don't have to use

> > conversions to intermix them.

>

> No, closely related means I can use

> a cast instead of a conversion as in:

>

> unsigned(DataOutReg) /= CTPCurCmd(DAT_RNG)

>

> Let's look up the "/=" functions available

> in the numeric_std source here:

>

> http://www.cs.umbc.edu/help/VHDL/pac...umeric_std.vhd

>

> function "/=" (L,R: UNSIGNED ) return BOOLEAN;

> function "/=" ( L,R: SIGNED) return BOOLEAN;

> function "/=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;

> function "/=" ( L: INTEGER; R: SIGNED) return BOOLEAN;

> function "/=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;

> function "/=" ( L: SIGNED; R: INTEGER) return BOOLEAN;

>

> For your example, a cast is needed to match the first signature.

>

> -- Mike Treseler
I have seen to_unsigned(), unsigned() and unsigned'. I understand

that the first to are conversion and type casting respectively. What

is the third called? I expect this is only for use where a literal or

expression can be interpreted more than one way and explains to the

tool what is intended, right?

I read back a bit and see that it is a "type qualification". I think

I got all that now. So even when types are closely related, you still

have to explicitly tell the tool to change the interpretation.

I think I wish I had started with Verilog instead of VHDL. At least

now if I start coding in Verilog, it will be an informed decision.

The little Verilog I have coded was very easy to do and I did it with

*no* additional training. I just picked up a little from a book and

the rest came pretty easy.

Does Verilog support user libraries in a similar manner to VHDL?

Rick