Shift register extraction fails

Hi!

I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
Spartan 3E. I'm down to copying this code:

entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;

from the xilinx website:
http://toolbox.xilinx.com/docsan/3_1...2/xst02007.htm

But still, ISE synthesizes D-Flipflops:
Synthesizing Unit <shift>.
Related source file is "...".
Found 8-bit register for signal <tmp>.
Summary:
inferred 8 D-type flip-flop(s).
Unit <shift> synthesized.

And yes, Shift register extraction and logical shifter extraction in the
HDL options are checked.

Please, help me before I go mad...

- Philip
--
Machen Sie sich erst einmal unbeliebt, dann werden
Sie auch ernst genommen. (Konrad Adenauer)

Philip Herzog

"Philip Herzog" <> wrote in message
news:...
> Hi!
>
> I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
> Spartan 3E. I'm down to copying this code:
>
>
> And yes, Shift register extraction and logical shifter extraction in the
> HDL options are checked.
>
> Please, help me before I go mad...
>
> - Philip
> --
> Machen Sie sich erst einmal unbeliebt, dann werden
> Sie auch ernst genommen. (Konrad Adenauer)
>
Hi Philip,

Does this work? :-

tmp <= tmp(6 downto 0) & SI;

HTH., Syms.

Symon

Symon wrote:
> Does this work? :-
> tmp <= tmp(6 downto 0) & SI;

Nope, tried that too...

- Philip
--
Machen Sie sich erst einmal unbeliebt, dann werden
Sie auch ernst genommen. (Konrad Adenauer)

Philip Herzog

Brian Drummond wrote:
> Does the synthesiser recognise the preferred
> if rising_edge(C) then
> instead?

Yes, that's what I usually use. I just copied this example from the
xilinx web page because that was the example they gave for shift
register extraction.

- Philip
--
Machen Sie sich erst einmal unbeliebt, dann werden
Sie auch ernst genommen. (Konrad Adenauer)

Philip Herzog

Philip,
Webcase?
Syms.

Symon

Philip Herzog wrote:
> I'm trying to get Xilinx ISE 9.2 to synthesize a shift register
> But still, ISE synthesizes D-Flipflops:
> Synthesizing Unit <shift>.
> Related source file is "...".
> Found 8-bit register for signal <tmp>.
> Summary:
> inferred 8 D-type flip-flop(s).

> And yes, Shift register extraction and logical shifter extraction in the
> HDL options are checked.
>
> Please, help me before I go mad...

Maybe those 8 flops are wired up like a shift register.
Have a look on the RTL viewer.

Note that all the fpga really has is luts and flops.
A shift register is an abstraction.

-- Mike Treseler

Mike Treseler

It looks like that part only supports a 16-bit shift register in a LUT.

jens

"jens" <> wrote in message
news:1e501aec-c334-46b3-89a5-...
> It looks like that part only supports a 16-bit shift register in a LUT.

No,
UG331
Fig.7.2.
Syms.

Symon

Mike Treseler wrote:
> Maybe those 8 flops are wired up like a shift register.

I'm pretty sure they were, but that's the whole point: That uses 8
flops, but if the shift register was extracted and packed into a LUT I'd
only use one LUT. This makes a difference for me, since I need many of
them...

- Philip
--
I will always be puzzled by the human predilection
for piloting vehicles at unsafe velocities.
(Lieutenant Commander Data)

Philip Herzog

On 30 May, 08:29, Philip Herzog <p...@arcor.de> wrote:
> Mike Treseler wrote:
> > Maybe those 8 flops are wired up like a shift register.
>
> I'm pretty sure they were, but that's the whole point: That uses 8
> flops, but if the shift register was extracted and packed into a LUT I'd
> only use one LUT. This makes a difference for me, since I need many of
> them...
>
> - Philip
> --
> I will always be puzzled by the human predilection
> for piloting vehicles at unsafe velocities.
> (Lieutenant Commander Data)

A LUT "shift register" as you call it is not actually a shift
register, rather it is a delay function. You cannnot tap off it. The
Unisim library contains an element "SRL16", which will implement a 1
bit shift register that takes 1 lut, with a delay of between 1 and 16
clock cycles. It uses 1 Lut and 1 register.

The problem with delcaring it as a vector of length 16, it implies
each bit is a register, and you have access to each bit individually.
Unless the synthesiser analyses the registers and finds none of them
are tapped, and is clever enough, it will most likely create a string
of registers.

Tricky