HDL - simulation vs synthesis

I run Xilinx ISE v10.1 and use VHDL. I have put together a fairly
small circuit that merely sends out solid colors and sync signals on a
VGA line. During the active video portion of time, a color should
show up on the screen. The color depends on which of three switches
on my development board are turned on. There is one for red, green
and blue.

Now the behavioral simulation tells me that the code works exactly as
it is supposed to, however, when I actually implement it on my
development board it does not work. I have heard of this type of
problem many times, but have no idea where to begin in finding the
fault.

Just so nobody thinks I'm trying too much at once, I did try it
without the switches and told it to just output a solid, unchanging,
color. That worked. I tested it for each of the three colors.

The RTL schematic that is generated by ISE shows me that both the
three switches and the red_out, green_out, and blue_out do not exist,
but none of the warning messages that show up tell me that they were
removed. Can somebody tell me where to begin in solving this issue?
Perhaps a list of things to try / look for or link me to some possible
solution or list of solutions.

digital pig

[digital pig]

Problem solved. Thanks to those who helped me elsewhere.

http://groups.google.com/group/comp....4101556bb8293#

digital pig