generic maps based on an input signal

Hi all,

I am trying to build a block whose component ports' length depend on an input. However I have problems which I honestly cannot solve.

myBlock will accept an input 'count'. This will then be converted to an integer. From that integer, the 256-bit input will be sliced. So the length of bits that will enter subBlock will only be the input bits running from that
integer downto 0. While the length of subOut will be half the length of subIn.


Below is the code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity myBlock is

generic (x : natural :=16;

y : natural := 32;
z : natural := 5);

port (clk, rst : in std_logic;

count : in std_logic_vector (z-1 downto 0);--THIS WILL BE CONVERTED TO INTEGER
input : in std_logic_vector (y-1 downto 0);
output : out std_logic_vector (x-1 downto 0));

end myBlock;

architecture bhv of myBlock is

component subBlock
generic (a : positive;

b : positive);

port (clk, rst : in std_logic;

subIn : in std_logic_vector (a-1 downto 0);
subOut : out std_logic_vector (b-1 downto 0));

end component;

signal q, q2 : integer;

begin

q <= conv_integer (count);
q2 <= q/2;

subBlock generic map (a=>q2, b=>q)

port map (clk, rst, input, output)

end bhv;



Such code above gave me the following errors:

The actual value (Signal 'q2') associated with a generic must be a globally static expression.
The actual value (Signal 'q') associated with a generic must be a globally static expression.

Try as I might I really don't know how to make q and q2 global statics. What do I do now?

Many thanks,
tahder

tahder

[tahder]

I'm sorry I had already posted my question above when I read this thread
http://www.velocityreviews.com/forum...-changing.html

However, the block I am trying to implement has several subblocks so I do component instantiation because I felt it is manageable and good for reuse. There is no process in my architecture body.

Thanks again,
tahder

tahder