Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Multiplier synthesis on vhdl

Reply
Thread Tools

Multiplier synthesis on vhdl

 
 
zenerz zenerz is offline
Junior Member
Join Date: May 2008
Posts: 1
 
      05-25-2008
Hello!

Got a huge problem with a design. Im working on a project with a spartan 3 3s200ft256 and this fpga has 12 multipliers of 18x18. Well the question is all about this line of code...
Img_addr<= std_logic_vector(Img_size_x * std_logic_vector(to_unsigned( j+ n, 8 ))+m + k -1);

img_size_x is std_logic_vector, j, n, m, k are integer variables on a process.
(8 bits slv * 8 bits slv)

Does this sentence infers one multiplier on synthesis?. The functional model is ok, but dunno if im going to find error on synthesis. I read somewhere that Leonardo modgen automatically recognizes the operator * and infers and synthetises the multiplier.
Does Leonardo Spectrum do the "trick" or i have to declare the multiplier and instantiate it?

Please, help me out
 

Last edited by zenerz; 05-25-2008 at 11:15 PM..
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL code for multiplier chi_rulez VHDL 7 10-17-2011 02:21 PM
fixed point multiplier in VHDL Viswan VHDL 9 02-11-2004 09:00 PM
4527 (bcd rate multiplier) vhdl code Markus Fuchs VHDL 0 09-17-2003 02:18 PM
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed... walala VHDL 4 09-09-2003 08:41 AM
what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes walala VHDL 4 09-08-2003 01:51 PM



Advertisments