Does this 'structure' exist in VHDL

I'm somewhat new to VHDL so I'll try to explain what I want to do.

I'm using an evaluation board (from Lattice) and want to create a debounced signal to use with student labs, that I'll use in a course on Digital Logic.

I can create the debounced signal (I'll call it "DCLK") in a VHDL entity/architecture file that uses the proper pin numbers for the inputs of the switch (it is a spdt, so two inputs)..

But now I just want to use the output signal in other VHDL designs.. I don't want to have to instantiate a component.. port map the inputs, etc.

now in C it might be like using an "include" statement.. maybe I can do it using a subroutine?.. I simply want to use the output signal "DCLK" in future designs as easily as possible.

So I'm unsure of quite how to create this 'block'.. I want to have a separate file for the debounced switch that I include with my design (I'm using ispLever with Synplify), but just somehow access the output signal DCLK in my main VHDL lab file that I might be using at the time..

I have read quite a bit on components and instantiating components, but this is not really a component that I'll have multiple instances of. It is like have circuit A having a single signal (DCLK) feed circuit B and I want the two circuit descriptions in their own VHDL file.. And in the VHDL for circuit B I just want to use signal DCLK.. I am unsure how to include and use the Circuit A VHDL file.


Hope this makes some sense..

Dave Crabbe
Nova Scotia Community College

crabbedh