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Using a vector as an index

 
 
M. Hamed
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      05-22-2008
Why is the Xilinx tool complaining about this (VHDL):

timer_done <= timer(data_len);

Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
std_logic_vector.

I want the tool to automatically infer a MUX with data_len as the
selector and timer as the input.

I can use a CASE statement but that is a lot of coding. I think
Verilog can happily accept that.

Thanks.
 
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Dave
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      05-22-2008
On May 22, 3:40 pm, "M. Hamed" <(E-Mail Removed)> wrote:
> Why is the Xilinx tool complaining about this (VHDL):
>
> timer_done <= timer(data_len);
>
> Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
> std_logic_vector.
>
> I want the tool to automatically infer a MUX with data_len as the
> selector and timer as the input.
>
> I can use a CASE statement but that is a lot of coding. I think
> Verilog can happily accept that.
>
> Thanks.


Try this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- snip

timer_done <= timer(to_integer(unsigned(data_len));

Dave
 
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