|
|
|
|
|
|||||||
 |
VHDL - diference between signal and variable? |
|
|
Thread Tools | Search this Thread |
05-20-2008, 06:26 AM
|
#1 |
diference between signal and variable?
good morning
can someone explain me the diference between use a signal and a variable? is there a pysic diference between them both? jonathan castro |
|
|
|
|
05-20-2008, 12:17 PM
|
#2 |
|
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 245
|
Find and download Evita VHDL interactive book - In chapter 6 will you find examples which explains the difference.
A variable will get its value immediate with := A signal will wait until the code ended <= jeppe |
|
|
|
|
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Variable scope | toller | Hardware | 1 | 04-21-2008 08:28 PM |
| Need help on Modelsim VHDL syntax? ASAP:) | kaji | General Help Related Topics | 0 | 03-14-2007 10:43 PM |
| Need help on a Modelsim VHDL Syntax? ASAP:) | kaji | Software | 0 | 03-14-2007 10:43 PM |
| Need Help on a Modelsim VHDL Syntax....ASAP:) | kaji | Hardware | 0 | 03-14-2007 10:41 PM |
