«

Hello,


I need to build the digital frequency modulator and demodulator in
VHDL. I am using Spartan Chip. I have got 48 bits of data. The FPGA is
serial outing each bit at the rising edge of the 1.5MHz clock. I need
to send this data stream, Clock and Synch signal ( which goes high for
the time when FPGA is serial outing the data else stays low)
wirelessly to a receiver. The reciever or demodulator will send the
data, clock and synch signals to a DAC.

Can somebody give me some suggestions that How to proceed with this
project?

Thanks
John